In recent years, a nonvolatile memory device termed a flash EEPROM (Electrically Erasable Programmable Read Only Memory) from which data stored therein can be erased electrically simultaneously in specified units and in which data can be written electrically has drawn growing attention as a memory device for storing data and data for program composition. The flash EEPROM (hereinafter referred to as a flash memory) has a memory cell composed of an electrically erasable and writable nonvolatile memory element and it is possible to erase data or data for program composition once written in the memory cell therefrom and rewrite (program) new data or data for program composition in the memory cell.
Conventionally, the accumulation of charge in the flash memory has been performed by accumulating electrons in a floating gate electrode (floating gate electrode) composed of a polysilicon film and electrically insulated from its surroundings. This electron accumulating operation, i.e., a so-called write operation is performed normally by injecting hot electrons, while an erase operation which releases the accumulated electrons to the outside of the floating gate electrode is performed by using a tunnel current passing through a gate oxide film. When the writing and erasing are repeated, a charge trap is formed in the gate oxide film so that the density of surface states increases at the interface between the substrate and the gate oxide film. In particular, the former has am essential problem of degrading a charge retention property, i.e., a retention property after the rewriting.
As a method for eliminating the problem, there has been proposed a system which uses a nonconductive charge trap film for charge accumulation in an EEPROM. Examples of the system are disclosed in U.S. Pat. Nos. 5,768,192, 5,966,603, 6,011,725, and 6,180,538 and in “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge to Floating Gate Cell”, B. Eitan et al., International Conference On Solid State Devices and Materials, Tokyo, 1999.
As shown in FIG. 39 (diagrammatic cross-sectional view of a cell), e.g., the system disclosed in U.S. Pat. No. 5,768,192 uses, as a gate insulating film, a multilayer film having a so-called ONO (Oxide/Nitride/Oxide) structure in which a silicon nitride film 113 is interposed between insulating films 112 and 114 each composed of a silicon oxide film or the like, turns ON a transistor by applying 0 V to a source 117 and a proper positive voltage to each of a drain 116 and a control gate 115, injects hot electrons generated in the vicinity of the drain 116 such that the electrons are trapped in the foregoing silicon nitride film 113, and thereby performs writing. In the charge accumulating system, electron traps in the silicon nitride film 113 are discontinuous and discrete compared with those in the system which accumulates charge in a polysilicon film which is a continuous conductive film. Accordingly, there is no such situation in which the accumulated charge entirely dissipate even when a charge leakage path, such as a pinhole, occurs in a part of the oxide film 112 so that the system features an inherently reliable retention property.
On the other hand, U.S. Pat. No. 6,011,725 discloses a so-called multivalued cell technique which independently controls charge accumulation in two places in the vicinity of the drain 116 and in the vicinity of the source 117 by using the locality of hot electron injection and thereby implements 2-bit information in one cell, as shown in FIG. 40 (diagrammatic cross-sectional view of a cell).
A method for forming an ONO film is also disclosed in U.S. Pat. No. 5,966,603, which forms an ONO structure by, e.g., forming an ON multilayer film on a substrate and then oxidizing an upper portion of a silicon nitride film, or by forming an ONO multilayer film on a substrate, then adding an oxidation step, to introduce oxygen into the silicon nitride film, thereby improving the retention property of a memory cell.
A method for forming an ONO film by RTCVP (Rapid Thermal Chemical Vapor Deposition) is also claimed in U.S. Pat. No. 6,180,538, in which a temperature for the deposition of an oxide film is 700 to 800° C. and the thickness of the oxide film is 5 to 15 nm.